View EX1B28-FCS100I_462703.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

v3.0
eX Family FPGAs
Le a di n g E d ge P er f o r m a n ce
* 240 MHz System Performance * 3.9ns Clock-to-Out (Pad-to-Pad) * 350 MHz Internal Performance
Sp e ci f i c a t i on s
* Individual Output Slew Rate Control * 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength * Software Design Support with Actel Designer Series and Libero Tools * Up to 100% Resource Utilization with 100% Pin Locking * Deterministic Timing * Unique In-System Diagnostic and Verification Capability with Silicon Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Secure Programming Technology Prevents Reverse Engineering and Design Theft
G en er al D e sc r i p t i on
* 3,000 to 12,000 Available System Gates * As Many as 512 Maximum Flip-Flops (Using CC Macros) * 0.22 CMOS Process Technology * Up to 132 User-Programmable I/O Pins
Fe a t ur es
* High-Performance, Low-Power Antifuse FPGA * LP/Sleep Mode for Additional Power Savings * Advanced Small-footprint Packages * Hot-Swap Compliant I/Os * Single-Chip Solution * Nonvolatile * Live on power up * Power-Up/Down Friendly (No Sequencing Required for Supply Voltages) * Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power Up
eX P r o du ct Pr o f i l e
Device Capacity System Gates Typical Gates Register Cells (Dedicated Flip-Flops) Combinatorial Cells Maximum User I/Os Speed Grades Temperature Grades Package (by pin count) TQFP CSP
The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent low power attributes of the antifuse technology, coupled with an additional low static power mode, make these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22 CMOS antifuse technology, these devices achieve high performance with no power penalty.
eX64 3,000 2,000 64 128 84 -F, Std, -P C, I 64, 100 49, 128
eX128 6,000 4,000 128 256 100 -F, Std, -P C, I 64, 100 49, 128
eX256 12,000 8,000 256 512 132 -F, Std, -P C, I 100 128, 180
D e ce m b e r 2 0 0 1
1
(c) 2001 Actel Corporation
e X F a m il y F P GA s
O r d e r i n g I nf o r m a t i o n
eX128
-P
TQ
100
Application (Temperature Range) Blank = Commercial (0 to +70C) I = Industrial (-40 to +85C) PP = Pre-production Package Lead Count Package Type TQ = Thin (1.4mm) Quad Flat Pack CS = Chip-Scale Package (0.8mm pitch)
Speed Grade Blank = Standard Speed -P = Approximately 30% Faster than Standard -F = Approximately 40% Slower than Standard Part Number eX64 = eX128 = eX256 = 64 Dedicated Flip-Flops (3,000 System Gates) 128 Dedicated Flip-Flops (6,000 System Gates) 256 Dedicated Flip-Flops (12,000 System Gates)
Pr od uc t P l a n
Speed Grade -F eX64 Device 64-Pin Thin Quad Flat Pack (TQFP) 100-Pin Thin Quad Flat Pack (TQFP) 49-Pin Chip Scale Package (CSP) 128-Pin Chip Scale Package (CSP) eX128 Device 64-Pin Thin Quad Flat Pack (TQFP) 100-Pin Thin Quad Flat Pack (TQFP) 49-Pin Chip Scale Package (CSP) 128-Pin Chip Scale Package (CSP) eX256 Device 100-Pin Thin Quad Flat Pack (TQFP) 128-Pin Chip Scale Package (CSP) 180-Pin Chip Scale Package (CSP) Contact your Actel sales representative for product availability. Speed Grade: -P = Approx. 30% faster than Standard Availability: = -F = Approx. 40% slower than Standard Available Applications: Std -P Application C I
C = Commercial I = Industrial Only Std Speed Grade
Pl a s t i c D e vi c e Re so u r ce s
User I/Os (including clock buffers) Device eX64 eX128 eX256 Package Definitions: TQFP 64-Pin 41 46 TQFP 100-Pin 56 70 CSP 49-Pin 36 36 CSP 128-Pin 84 100 100 CSP 180-Pin -- -- 132
-- 81 -- TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
2
v3.0
e X F a m il y F P GA s
eX F am i l y A r c hi t e c t ur e
The eX family architecture uses a "sea-of-modules" structure where the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Interconnection among these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements. Actel's eX family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 1). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from either the hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions up to 5 inputs (Figure 2). Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the eX architecture.
M o d ule O r g a n i z a t io n
Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. The eX devices contain one type of Cluster, which contains two C-cells and one R-cell. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 3 on page 4). The eX devices contain one type of SuperClusters, which are two-wide groupings of one type of clusters.
S0
Routed Data Input S1 PSET
DirectConnect Input
D
Q
Y
HCLK CLKA, CLKB, Internal Logic CKS CKP CLR
Figure 1 * R-Cell
D0 D1 Y D2 D3 Sa Sb
DB A0 B0 A1 B1
Figure 2 * C-Cell
v3.0 3
e X F a m il y F P GA s
Rou ti ng Res our ces
Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 4). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns (-P speed grade).
FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.3 ns (-P speed grade). In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays.
R-Cell
Routed Data Input S1 D0 D1 PSET DirectConnect Input D2 D Q Y D3
C-Cell
S0
Y
Sa
Sb
HCLK CLKA, CLKB, Internal Logic CKS CKP CLR DB A0 B0 A1 B1
Cluster 1
Cluster 1
Type 1 SuperCluster
Figure 3 * Cluster Organization
Type 1 SuperClusters
DirectConnect * No antifuses * 0.1 ns routing delay
FastConnect * One antifuse * 0.3 ns routing delay
Routing Segments * Typically 2 antifuses * Max. 5 antifuses
Figure 4 * DirectConnect and FastConnect for Type 1 SuperClusters
4 v3.0
e X F a m il y F P GA s
Cl ock Res our ce s
Actel's high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-Cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 3.9ns clock-to-out (pad-to-pad) performance of the eX devices. The hard-wired clock is tuned to provide a clock skew of less than 0.1ns worst case. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the eX device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is sourced from internal logic signals then the external clock pin cannot be used for any other input and must be tied low or high. Figure 5 describes the clock circuit used for the constant load HCLK. Figure 6 describes the CLKA and CLKB circuit used in eX devices.
platform upon which to integrate the functionality previously contained in CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an eX device with dramatic improvements in cost and time to market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance.
I/O Modules
Each I/O on an eX device can be configured as an input, an output, a tristate output, or a bidirectional pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.9ns. I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in eX FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. See Table 1 for more information. Table 1 * I/O Features
Function Input Buffer Threshold Selection Flexible Output Driver Output Buffer Description * TTL/3.3V LVTTL
Constant Load Clock Network HCLKBUF
Figure 5 * eX HCLK Clock Pad
* 2.5V LVCMOS 2 * 3.3V LVTTL * 5.0V TTL/CMOS "Hot-Swap" Capability * I/O on an unpowered device does not sink current * Can be used for "cold sparing" Selectable on an individual I/O basis Individually selectable low-slew option
Clock Network
From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI
Figure 6 * eX Routed Clock Buffer
O t he r A r c hi t ec tu ral Fe atu r e s
T echno log y
Power Up
Individually selectable pull ups and pull downs during power up (default is to power up in tristate) Enables deterministic power up of device VCCA and VCCI can be powered in any order
Actel's eX family is implemented on a high-voltage twin-well CMOS process using 0.22 design rules. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25 with a capacitance of 1.0 fF for low signal impedance.
P erf orm a nce
Hot S wa ppin g
The combination of architectural features described above enables eX devices to operate with internal clock frequencies exceeding 350 MHz for very fast execution of complex logic functions. Thus, the eX family is an optimal
eX I/Os are configured to be hot swappable. During power up/down (or partial up/down), all I/Os are tristated. VCCA and VCCI do not have to be stable during power up/down, and they do not require a specific power-up or power-down sequence in order to avoid damage to the eX devices. After the eX device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip
v3.0
5
e X F a m il y F P GA s
operating conditions are reached. Please see the Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications application note for more information on hot swapping.
P ower R equ ir em ent s
The eX family supports mixed voltage operation and is designed to tolerate 5.0V inputs in each case (Table 2). Power consumption is extremely low due to the very short distances signals, which are required to travel to complete a circuit. Power requirements are further reduced because of the small number of low-resistance antifuses in the path. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power architecture FPGA available today. Also, when the device is in low power mode, the clock pins must not float. They must be driven either HIGH or LOW. We recommend that signals driving the clock pins be fixed at HIGH or LOW rather than toggle to achieve maximum power efficiency. Table 2 * Supply Voltages
Maximum Maximum Input Output Tolerance Drive 5.0V 5.0V 5.0V 2.5V 3.3V 5.0V
in conjunction with the program fuse. The functionality of each pin is described in Table 3. In the dedicated test mode, TCK, TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10k. TMS can be pulled LOW to initiate the test sequence. Table 3 * Boundary Scan Pin Functionality
Program Fuse Blown (Dedicated Test Mode) TCK, TDI, TDO are dedicated BST pins No need for pull-up resistor for TMS Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are flexible and may be used as I/Os Use a pull-up resistor of 10k on TMS
C onfi gur ing Di agn ost i c P in s
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and PRB) are placed in the desired mode by selecting the appropriate check boxes in the "Variation" dialog window. This dialog window is accessible through the Design Setup Wizard under the Tools menu in Actel's Designer software.
T RS T P i n
VCCA eX64 eX128 eX256 2.5V 2.5V 2.5V
VCCI 2.5V 3.3V 5.0V
When the "Reserve JTAG Reset" box is checked, the TRST pin will become a Boundary Scan Reset pin. In this mode, the TRST pin will function as an asynchronous, active-low input to initialize or reset the BST circuit. An internal pull-up resistor will be automatically enabled on the TRST pin. The TRST pin will function as a user I/O when the "Reserve JTAG Reset" box is not checked. The internal pull-up resistor will be disabled in this mode.
D edic at ed T e st M ode
Low P ower Mode
The new Actel eX family has been designed with a Low Power Mode. This feature, activated with a special LP pin, is particularly useful for battery-operated systems where battery life is a primary concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby current. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated when the device enters this mode. Since the core of the device is turned off, the states of the registers are lost. The device must be re-initialized when normal operating mode is achieved.
2.5V LP/Sleep Mode Specifications Typical Conditions, VCCA, VCCI = 2.5V, TJ = 25 C
When the "Reserve JTAG" box is checked, the eX device is placed in Dedicated Test mode, which configures the TDI, TCK, and TDO pins for BST or in-circuit verification with Silicon Explorer II. An internal pull-up resistor is automatically enabled on both the TMS and TDI pins. In Dedicated Test Mode, TCK, TDI, and TDO are dedicated test pins and become unavailable for pin assignment in the Pin Editor. The TMS pin will function as specified in the IEEE 1149.1 (JTAG) Specification.
Fl exi ble Mo de
Product eX64 eX128 eX256
Low Power Standby Current 100 111 134
Units A A A
Bou ndar y S can T es ti ng (BS T )
When the "Reserve JTAG" box is not selected (default setting in Designer software), eX is placed in Flexible mode, which allows the TDI, TCK, and TDO pins to function as user I/Os or BST pins. In this mode the internal pull-up resistors on the TMS and TDI pins are disabled. An external 10k pull-up resistor to VCCI is required on the TMS pin. The TDI, TCK, and TDO pins are transformed from user I/Os into BST pins when a rising edge on TCK is detected while TMS is at logical low. Once the BST pins are in test mode they will remain in BST mode until the internal BST state
v3.0
All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins
6
e X F a m il y F P GA s
machine reaches the "logic reset" state. At this point the BST pins will be released and will function as regular I/O pins. The "logic reset" state is reached five TCK cycles after the TMS pin is set to logical HIGH. The Program fuse determines whether the device is in Dedicated Test or Flexible mode. The default (fuse not programmed) is Flexible mode.
Dev el opm ent To ol S uppor t
verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds.
eX P ro be Cir cu it C ont ro l Pi ns
The eX devices are fully supported by Actel's line of FPGA development tools, including the Actel Designer Series suite and Libero, the FPGA design tool suite. Designer Series, Actel's suite of FPGA development tools for PCs and Workstations, includes the ACTgen Macro Builder, timing driven place-and-route, timing analysis tools, and fuse file generation. Libero is a design management environment that integrates the needed design tools, streamlines the design flow, manages all design and log files, and passes necessary design data between tools. Libero includes Synplify, ViewDraw, Actel's Designer Series, ModelSim HDL Simulator, WaveFormer Lite, and Actel Silicon Explorer. In addition, the eX devices contain internal probe circuitry that provides built-in access to the output of every C-cell, R-cell, and routed clock in the design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy-to-use integrated
Channels
The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 7 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification. The TRST pin is equipped with an internal pull-up resistor. To remove the boundary scan state machine from the reset state during probing, it is recommended that the TRST pin be left floating.
De si gn C ons id era ti ons
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Because these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the Security Fuse should not be programmed because doing so disables the probe circuitry.
16
eX FPGA TDI TCK TMS Serial Connection Silicon Explorer II TDO
PRA PRB
Figure 7 * Probe Setup
v3.0
7
e X F a m il y F P GA s
2. 5 V / 3. 3 V / 5. 0 V O p er a t i n g C on di t i on s
Abs ol ut e M axim u m Ra ti ngs 1
R ecom m en ded Oper at ing C ondi ti ons
Parameter Limits Units V V V V C Temperature Range1 2.5V Power Supply Range (VCCA, VCCI) 3.3V Power Supply Range (VCCI) 5.0V Power Supply Range (VCCI)
Commercial 0 to +70 2.3-2.7 3.0-3.6 4.75-5.25
Industrial -40 to +85 2.3-2.7 3.0-3.6 4.5-5.5
Units C V V V
Symbol VCCI VCCA VI VO TSTG
Parameter DC Supply Voltage DC Supply Voltage Input Voltage Output Voltage Storage Temperature
-0.3 to +6.0 -0.3 to +3.0 -0.5 to +5.5 -0.5 to +VCCI + 0.5 -65 to +150
Note: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.
T ypi cal eX S t andb y Cur r ent at 25 C
Note: 1. Ambient temperature (TA).
Product eX64 eX128 eX256
2.5 V El ect r ical S pe cif i cat io ns
VCCA= 2.5V VCCI = 2.5V 397A 696A 698A
VCCA = 2.5V VCCI = 3.3V 497A 795A 796A
Commercial Symbol Parameter VDD = MIN, VI = VIH or VIL VOH VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VOL VIL VIH IOZ tR, tF CIO ICC IV
3,4 1,2
Industrial Min. 2.1 2.0 1.7 Max. Units V V V 0.2 0.4 0.7 -0.3 0.7 V V V V V A ns pF mA
Min. (IOH = -100A) 2.1 (IOH = -1 mA) (IOH = -2 mA) (IOL= 100A) (IOL= 1mA) (IOL= 2 mA) -0.3 2.0 1.7
Max.
0.2 0.4 0.7 0.7
VDD = MIN, VI = VIH or VIL VDD = MIN,VI = VIH or VIL Input Low Voltage, VOUT VVOL(max) Input High Voltage, VOUT VVOH(min) 3-State Output Leakage Current, VOUT = VCCI or GND Input Transition Time tR, tF I/O Capacitance Standby Current
1.7 VDD + 0.3 1.7 VDD + 0.3 -10 10 10 10 1.0 -10 10 10 10 3.0
Curve5
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes: 1. tR is the transition time from 0.7 V to 1.7V. 2. tF is the transition time from 1.7V to 0.7V. 3. ICC max Commercial -F = 5.0mA 4. ICC=ICCI + ICCA
8
v3.0
e X F a m il y F P GA s
3.3 V El ect r ica l S pe cif i cat io ns
Commercial Symbol VOH VOL VIL VIH IIL/ IIH IOZ tR, tF CIO ICC
3,4 1,2
Industrial Min. 0.9 VCCI 2.4 Max. Units V V 0.1 VCCI 0.4 0.8 2.0 -10 -10 10 10 10 10 10 V V V V A A ns pF mA
Parameter VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND 3-State Output Leakage Current, VOUT = VCCI or GND Input Transition Time tR, tF I/O Capacitance Standby Current
Min. (IOH = -1mA) 0.9 VCCI (IOH = -8mA) 2.4 (IOL= 1mA) (IOL= 12mA) 2.0 -10 -10
Max.
0.1 VCCI 0.4 0.8 10 10 10 10 1.5
IV Curve5 Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html. Notes: 1. tR is the transition time from 0.8 V to 2.0V. 2. tF is the transition time from 2.0V to 0.8V. 3. ICC max Commercial -F=5.0mA 4. ICC=ICCI + ICCA
5.0V Electrical Specifications
Commercial Symbol VOH VOL VIL VIH IIL/ IIH IOZ tR, tF CIO ICC3,4 IV Curve5
1,2
Industrial Min. 0.9 VCCI 2.4 Max. Units V V 0.1 VCCI 0.4 0.8 2.0 -10 -10 10 10 10 10 20 V V V V A A ns pF mA
Parameter VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND 3-State Output Leakage Current, VOUT = VCCI or GND Input Transition Time tR, tF I/O Capacitance Standby Current
Min. (IOH = -1mA) 0.9 VCCI (IOH = -8mA) (IOL= 1mA) (IOL= 12mA) 2.0 -10 -10 2.4
Max.
0.1 VCCI 0.4 0.8 10 10 10 10 15
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html
Notes: 1. tR is the transition time from 0.8 V to 2.0V. 2. tF is the transition time from 2.0V to 0.8V. 3. ICC max Commercial -F=20mA 4. ICC=ICCI + ICCA
v3.0
9
e X F a m il y F P GA s
eX D yna m ic P ower C ons um pt io n - Hi gh F re quenc y
300 250 Power (mW) 200 150 100 50 0 50 100 150 200 Frequency (MHz) eX64 eX128 eX256
Notes: 1. Device filled with 16-bit counters. 2. VCCA, VCCI = 2.7V, device tested at room temperature.
eX D yna m ic P ower C ons um pt io n - Low Fr eq uency
80 70 60 Power (mW) 50 40 30 20 10 0 0 10 20 30 40 50 Frequency (MHz) eX64 eX128 eX256
Notes: 1. Device filled with 16-bit counters. 2. VCCA, VCCI = 2.7V, device tested at room temperature.
10
v3.0
e X F a m il y F P GA s
T ota l Dy nam ic P owe r ( m W )
180 160
Total Dynamic Power (mW)
140 120 100 80 60 40 20 0 0 25 50 75 100 125 150 175 200 32-bit Decoder 8 x 8-bit Counters SDRAM Controller
Frequency (MHz)
S ys te m P owe r at 5% , 10 %, a nd 1 5% D ut y Cy cle
12,000 10,000
System Power (uW)
8,000 5% DC 6,000 4,000 2,000 0 0 10 20 30 40 50 60 10% DC 15% DC
Frequency (MHz)
v3.0
11
e X F a m il y F P GA s
Ju n ct i o n Te m p er a t u r e ( T J )
The temperature variable in the Designer Series software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Equation 1, shown below, can be used to calculate junction temperature. Junction Temperature = T + Ta Where: Ta = Ambient Temperature (1)
ja = Junction to ambient of package. ja numbers are located in the Package Thermal Characteristics section below.
P ac k ag e T h er m al C h ar a c t er i st i c s
The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. The maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a TQFP 100-pin package at commercial temperature and still air is as follows:
T = Temperature gradient between junction (silicon) and ambient T = ja * P
P = Power
Max. junction temp. (C) - Max. ambient temp. (C) 150C - 70C Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.1W ja (C/W) 37.5C/W ja Still Air 51.2 37.5 71.3 54.1 57.8 ja 300 ft/min 35 30 56.0 47.8 51
Package Type Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Chip Scale Package (CSP) Chip Scale Package (CSP) Chip Scale Package (CSP)
Pin Count 64 100 49 128 180
jc 14 12 3 3 3
Units C/W C/W C/W C/W C/W
12
v3.0
e X F a m il y F P GA s
eX T i m i n g M o de l *
Input Delays
Internal Delays Combinatorial Cell
Predicted Routing Delays
Output Delays
I/O Module t INYH = 0.7 ns
t IRD1 = 0.3 ns t IRD2 = 0.4 ns
I/O Module
t PD = 0.7 ns
t RD1 = 0.3 ns t RD4 = 0.7 ns t RD8 = 1.2 ns I/O Module
t DHL = 2.6 ns
Register Cell t ENZL= 1.9 ns t SUD = 0.5 ns t HD = 0.0 ns Routed Clock D Q t RD1 = 0.3 ns t DHL = 2.6 ns
t RCKH = 1.3 ns (100% Load)
t RCO= 0.6 ns Register Cell t IRD1 = 0.3 ns t SUD = 0.5ns t HD = 0.0 ns D Q t RD1 = 0.3 ns
I/O Module
I/O Module t INYH = 0.7 ns
t ENZL= 1.9 ns
t DHL = 2.6 ns
Hard-Wired Clock
t HCKH = 1.1 ns
t RCO= 0.6 ns
*Values shown for eX128-P, worst-case commercial conditions (5.0V, 35pF Pad Load).
H ar d-W i re d C loc k Ro ute d C loc k
External Setup = tINYH + tIRD1 + tSUD - tHCKH = 0.7 + 0.3 + 0.5 - 1.1 = 0.4 ns Clock-to-Out (Pad-to-Pad), typical = tHCKH + tRCO + tRD1 + tDHL = 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
External Setup = tINYH + tIRD2 + tSUD - tRCKH = 0.7 + 0.4 + 0.5 - 1.3= 0.3 ns Clock-to-Out (Pad-to-Pad), typical = tRCKH + tRCO + tRD1 + tDHL = 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
v3.0
13
e X F a m il y F P GA s
O ut p u t B uf f e r D e l ay s
E D TRIBUFF PAD To AC test loads (shown below)
VCC In Out VOL tDLH 50% 50% VOH 1.5V tDHL GND 1.5V En Out
VCC 50% VCC 50% 1.5V VOL tENZL tENLZ GND 10% En Out GND
VCC 50% 50% VOH 1.5V tENZH tENHZ GND 90%
A C T e st L oa d s
Load 1 (Used to measure propagation delay) To the output under test 35 pF To the output under test Load 2 (Used to measure enable delays) VCC GND Load 3 (Used to measure disable delays) VCC GND
R to VCC for tPZL R to GND for tPZH R = 1 k 35 pF
To the output under test
R to VCC for tPLZ R to GND for tPHZ R = 1 k 5 pF
I n pu t B uf f er D e l ay s
C- C e l l D el a ys
PAD
INBUF
Y
S A B VCC
Y
3V In Out GND 1.5V 1.5V VCC 50% 0V 50%
S, A or B Out GND Out
50% 50% VCC 50% tPD 50% tPD tPD
GND 50%
VCC GND tPD 50%
14
v3.0
e X F a m il y F P GA s
C el l T i m i n g C h ar a c t er i st i c s
Fl ip- Flo ps
D CLK
PRESET CLR
Q
(Positive edge triggered) tHD D tSUD CLK tHPWH, tRPWH tHPWL, tRPWL tHP
tRCO Q
tCLR CLR tWASYN PRESET
tPRESET
Ti m i ng C ha r a ct e r i s t i c s
Long T r acks
Timing characteristics for eX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all eX family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays.
Cr it ic al Net s and T ypi cal Ne ts
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, no more than six percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays.
T im in g D er at ing
Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to six percent of the nets in a design may be designated as critical.
eX devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing.
Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s
( N or m ali z ed to W or st - Cas e Com m er ci al, T J = 70 C, V C C A = 2.3 V)
Junction Temperature (TJ) VCCA 2.3 2.5 2.7 -55 0.75 0.70 0.66 -40 0.79 0.74 0.69 0 0.88 0.82 0.79 25 0.89 0.83 0.79 70 1.00 0.93 0.88 85 1.04 0.97 0.92 125 1.16 1.08 1.02
v3.0
15
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s
( W or st -C as e C om m er cia l Cond it ion s, V C C A = 2.3 V , T J = 70C )
`-P' Speed Parameter Description Delays1 0.7 Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
C-Cell Propagation tPD tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tINYH tINYL tINYH tINYL tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8
Internal Array Module
2
1.0
1.4
ns
Predicted Routing Delays
FO=1 Routing Delay, DirectConnect FO=1 Routing Delay, FastConnect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
0.1 0.3 0.3 0.4 0.5 0.7 1.2 1.7
0.1 0.5 0.5 0.6 0.8 1.0 1.7 2.5
0.2 0.7 0.7 0.8 1.1 1.3 2.4 3.5
ns ns ns ns ns ns ns ns
Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Hold Time 0.5 0.0 1.3 0.3 0.3
0.6 0.6 0.7 0.7 0.0 1.9 0.5 0.5
0.9 0.8 0.9 1.0 0.0 2.6 0.7 0.7
1.3 1.2 1.3
ns ns ns ns ns ns ns ns
2.5V Input Module Propagation Delays Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW 0.6 0.8 0.9 1.1 1.3 1.5 ns ns
3.3V Input Module Propagation Delays Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW 0.7 0.9 1.0 1.3 1.4 1.8 ns ns
5.0V Input Module Propagation Delays Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW 0.7 0.9 1.0 1.3 1.4 1.8 ns ns
Input Module Predicted Routing Delays2 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.3 0.4 0.5 0.7 1.2 0.4 0.6 0.8 1.0 1.7 0.5 0.8 1.1 1.3 2.4 ns ns ns ns ns
tIRD12 FO=12 Routing Delay 1.7 2.5 3.5 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
16
v3.0
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s (Continued)
( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C )
`-P' Speed Parameter Description Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 <0.1 4.0 250 1.1 1.1 2.0 2.0 <0.1 5.6 178 1.6 1.6 2.8 2.8 <0.1 2.3 2.3 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW1 tRCKSW1 tRCKSW1 Input LOW to HIGH (Light Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (Light Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (50% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (50% Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (100% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (100% Load) (Pad to R-Cell Input) MAX. Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 0.2 0.1 0.1 1.1 1.0 1.2 1.2 1.3 1.3 2.1 2.1 0.3 0.2 0.1 1.6 1.4 1.7 1.7 1.9 1.9 3.0 3.0 0.4 0.3 0.2 2.2 2.0 2.4 2.4 2.6 2.6 ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Clock skew improves as the clock network becomes more heavily loaded.
v3.0
17
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s (Continued)
( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2. 3V or 3 .0V , T J = 70 C )
`-P' Speed Parameter Description Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 <0.1 4.0 250 1.1 1.1 2.0 2.0 <0.1 5.6 178 1.6 1.6 2.8 2.8 <0.1 2.3 2.3 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW
1 1 1
Input LOW to HIGH (Light Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (Light Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (50% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (50% Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (100% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (100% Load) (Pad to R-Cell Input) MAX. Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4
1.0 1.0 1.2 1.2 1.4 1.4 2.0 2.0 0.2 0.2 0.1
1.4 1.4 1.7 1.7 2.0 2.0 2.8 2.8 0.3 0.2 0.1
2.0 2.0 2.4 2.4 2.8 2.8
ns ns ns ns ns ns ns ns
0.4 0.3 0.2
ns ns ns
Note: 1. Clock skew improves as the clock network becomes more heavily loaded.
18
v3.0
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s (Continued)
(Worst-Case Commercial Conditions V CCA = 2.3V, T J = 70C)
`-P' Speed Parameter Description Timing1 (VCCI = 2.3V) 3.3 3.5 11.6 2.5 11.8 3.4 2.1 2.4 0.034 0.016 0.05 Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
2.5V LVTTL Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--Low Slew Enable-to-Pad, Z to L Enable-to-Pad Z to L--Low Slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Delay vs. Load LOW to HIGH Delta Delay vs. Load HIGH to LOW Delta Delay vs. Load HIGH to LOW--Low Slew
4.7 5.0 16.6 3.6 16.9 4.9 3.0 5.67 0.046 0.022 0.072
6.6 7.0 23.2 5.1 23.7 6.9 4.2 7.94 0.066 0.05 0.1
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
3.3V LVTTL Output Module Timing1 (VCCI = 3.0V) tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--Low Slew Enable-to-Pad, Z to L Enable-to-Pad Z to L--Low Slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Delay vs. Load LOW to HIGH Delta Delay vs. Load HIGH to LOW Delta Delay vs. Load HIGH to LOW--Low Slew 2.8 2.7 9.7 2.2 9.7 2.8 2.8 2.6 0.02 0.016 0.05 4.0 3.9 13.9 3.2 13.9 4.0 4.0 3.8 0.03 0.022 0.072 5.6 5.4 19.5 4.4 19.6 5.6 5.6 5.3 0.046 0.05 0.1 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
5.0V TTL Output Module Timing1 (VCCI = 4.75V) tDLH tDHL tDHLS tENZL tENZLS tENZH Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--Low Slew Enable-to-Pad, Z to L Enable-to-Pad Z to L--Low Slew Enable-to-Pad, Z to H 2.0 2.6 6.8 1.9 6.8 2.1 3.3 2.9 3.7 9.7 2.7 9.8 3.0 4.8 4.0 5.2 13.6 3.8 13.7 4.1 6.6 ns ns ns ns ns ns ns
tENLZ Enable-to-Pad, L to Z Note: 1. Delays based on 35 pF loading.
v3.0
19
e X F a m il y F P GA s
Pi n D es c r i pt i on
CLKA/B Clock A and B TCK, I/O Test Clock
These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL or LVTTL specifications. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating.
GND Ground
Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 3 on page 6). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDI, I/O Test Data Input
LOW supply voltage.
HCLK Dedicated (Hard-wired) Array Clock
This pin is the clock input for sequential modules. Input levels are compatible with standard TTL or LVTTL specifications. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating.
I/O Input/Output
Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 3 on page 6). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDO, I/O Test Data Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL or LVTTL specifications. Unused I/O pins are automatically tristated by the Designer Series software.
LP Low Power Pin
Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 3 on page 6). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer is being used, TDO will act as an output when the "checksum" command is run. It will return to user IO when "checksum" is complete.
TMS Test Mode Select
Controls the low power mode of the eX devices. The device is placed in the low power mode by connecting the LP pin to logic high. In low power mode, all I/Os are tristated, all input buffers are turned OFF, and the core of the devices is turned OFF. To exit the low power mode, the LP pin must be set LOW. The device enters the low power mode 800ns after the LP pin is driven to a logic HIGH. It will resume normal operation in 200s after the LP pin is driven to a logic low. The logic high level on the LP pin must never exceed the VSV voltage. Refer to the VSV pin description.
NC No Connection
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 3 on page 6). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications.
TRST, I/O Boundary Scan Reset Pin
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
PRA, I/O PRB, I/O Probe A/B
Once it is configured as the JTAG Reset pin, the TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. This pin functions as an I/O when the "Reserve JTAG Reset Pin" is not selected in Designer.
V C CI Supply Voltage
The Probe pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality.
Supply voltage for I/Os. See Table 2 on page 6.
V C CA Supply Voltage
Supply voltage for Array. See Table 2 on page 6.
VSV Programming Voltage
Supply voltage used for device programming. This pin can be tied to VCCA or VCCI but cannot exceed 3.6V. If the security fuse is programmed, the VSV limit is extended to 6.0V.
20
v3.0
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s
64- Pi n TQ F P (T op Vi ew)
64 1
64-Pin TQFP
v3.0
21
e X F a m il y F P GA s
64- Pi n TQ F P
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
eX64 Function
eX128 Function
Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
eX64 Function
eX128 Function
GND TDI, I/O I/O TMS GND VCCI I/O I/O NC NC TRST, I/O I/O NC GND I/O I/O I/O I/O VCCI I/O PRB, I/O VCCA GND I/O HCLK I/O I/O I/O I/O I/O I/O
GND TDI, I/O I/O TMS GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O GND I/O I/O I/O I/O VCCI I/O PRB, I/O VCCA GND I/O HCLK I/O I/O I/O I/O I/O I/O
GND I/O I/O VSV1 VCCI I/O I/O NC NC I/O I/O VCCA GND/LP1 GND I/O I/O I/O I/O I/O VCCI I/O I/O CLKA CLKB VCCA GND PRA, I/O I/O VCCI I/O I/O TCK, I/O
GND I/O I/O VSV1 VCCI I/O I/O I/O I/O I/O I/O VCCA GND/ LP1 GND I/O I/O I/O I/O I/O VCCI I/O I/O CLKA CLKB VCCA GND PRA, I/O I/O VCCI I/O I/O TCK, I/O
1.
32 TDO, I/O TDO, I/O Please read the VSV and LP pin descriptions for restrictions on their use.
22
v3.0
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
1 0 0 -P in T QF P ( To p V ie w )
100 1
100-Pin TQFP
v3.0
23
e X F a m il y F P GA s
100- T Q FP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 eX64 Function GND TDI, I/O NC NC NC I/O TMS VCCI GND NC NC I/O NC I/O NC TRST, I/O NC I/O NC VCCI I/O NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O NC eX128 Function GND TDI, I/O NC NC NC I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O eX256 Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 eX64 Function GND NC NC NC I/O I/O eX128 Function GND NC NC NC I/O I/O eX256 Function GND I/O I/O I/O I/O I/O
VSV1
VCCI NC I/O NC I/O NC I/O NC I/O VCCA GND/LP1 GND I/O I/O NC NC NC NC NC I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O
VSV1
VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND/LP1 GND I/O I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O
VSV1
VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND/LP1 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O
1.
Please read the VSV and LP pin descriptions for restrictions on their use.
24
v3.0
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
49- Pi n CS P ( T op V ie w)
A1 Ball Pad Corner
1 A B C D E F G
2
3
4
5
6
7
49- Pi n CS P
Pin Number
eX64 Function
eX128 Function
Pin Number
eX64 Function
eX128 Function
A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 1.
I/O I/O I/O I/O VCCA I/O I/O TCK, I/O I/O I/O PRA, I/O CLKA I/O GND/LP1 I/O TDI, I/O VCCI GND CLKB VCCA I/O I/O TMS GND
I/O I/O I/O I/O VCCA I/O I/O TCK, I/O I/O I/O PRA, I/O CLKA I/O GND/LP1 I/O TDI, I/O VCCI GND CLKB VCCA I/O I/O TMS GND
D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7
VSV1 I/O I/O I/O TRST, I/O VCCI GND I/O I/O VCCI I/O I/O I/O I/O HCLK I/O TDO, I/O I/O I/O I/O PRB, I/O VCCA I/O I/O
VSV1 I/O I/O I/O TRST, I/O VCCI GND I/O I/O VCCI I/O I/O I/O I/O HCLK I/O TDO, I/O I/O I/O I/O PRB, I/O VCCA I/O I/O
D4 GND GND Please read the VSV and LP pin descriptions for restrictions on their use.
v3.0
25
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
128- P in CS P ( T op Vie w)
A1 Ball Pad Corner
1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12
26
v3.0
e X F a m il y F P GA s
128- CS P
Pin Number eX64 Function eX128 Function eX256 Function Pin Number eX64 Function eX128 Function eX256 Function
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3
I/O TCK, I/O VCCI I/O I/O VCCA I/O I/O VCCI I/O I/O I/O TMS I/O I/O I/O I/O PRA, I/O CLKB I/O I/O I/O GND I/O I/O TDI, I/O I/O I/O I/O CLKA I/O I/O I/O NC NC I/O NC I/O I/O
I/O TCK, I/O VCCI I/O I/O VCCA I/O I/O VCCI I/O I/O I/O TMS I/O I/O I/O I/O PRA, I/O CLKB I/O I/O I/O GND I/O I/O TDI, I/O I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O TCK, I/O VCCI I/O I/O VCCA I/O I/O VCCI I/O I/O I/O TMS I/O I/O I/O I/O PRA, I/O CLKB I/O I/O I/O GND I/O I/O TDI, I/O I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O
D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E9 E10 E11 E12 F1 F2 F3 F4 F9 F10 F11 F12 G1 G2 G3 G4 G9 G10 G11 G12 H1 H2 H3 H4 H9 H10
I/O I/O GND I/O GND I/O I/O I/O VCCI NC VCCI I/O GND GND I/O GND/LP1 VCCA NC NC NC I/O GND NC I/O I/O NC TRST, I/O I/O GND GND NC I/O NC GND I/O VCCI GND I/O VCCI
I/O I/O GND I/O GND I/O I/O I/O VCCI I/O VCCI I/O GND GND I/O GND/LP1 VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O TRST, I/O I/O GND GND I/O I/O I/O GND I/O VCCI GND I/O VCCI
I/O I/O GND I/O GND I/O I/O I/O VCCI I/O VCCI I/O GND GND I/O GND/LP1 VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O TRST, I/O I/O GND GND I/O I/O I/O GND I/O VCCI GND I/O VCCI
v3.0
27
e X F a m il y F P GA s
128- CS P
Pin Number eX64 Function eX128 Function eX256 Function Pin Number eX64 Function eX128 Function eX256 Function
H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 1.
VSV1 NC NC I/O VCCI I/O I/O I/O GND I/O GND I/O I/O NC NC I/O I/O I/O I/O PRB, I/O HCLK I/O I/O I/O TDO, I/O
VSV1 I/O NC I/O VCCI I/O I/O I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O HCLK I/O I/O I/O TDO, I/O
VSV1 I/O VSV I/O VCCI I/O I/O I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O HCLK I/O I/O I/O TDO, I/O
1
K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O NC VCCI GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O
Please read the VSV and LP pin descriptions for restrictions on their use.
28
v3.0
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
180- P in CS P ( T op Vi ew)
A1 Ball Pad Corner 1 A B C D E F G H J K L M N P 2 3 4 5 6 7 8 9 10 11 12 13 14
v3.0
29
e X F a m il y F P GA s
180- P in CS P
Pin Number eX256 Function Pin Number eX256 Function Pin Number eX256 Function Pin Number eX256 Function
1.
A1 I/O D6 I/O A2 I/O D7 CLKA A3 GND D8 I/O A4 NC D9 I/O A5 NC D10 I/O A6 NC D11 I/O A7 NC D12 I/O A8 NC D13 I/O A9 NC D14 I/O A10 NC E1 I/O A11 NC E2 I/O A12 I/O E3 I/O A13 I/O E4 I/O A14 I/O E5 I/O B1 I/O E6 I/O B2 I/O E7 GND B3 TCK, I/O E8 I/O B4 VCCI E9 GND B5 I/O E10 I/O B6 I/O E11 I/O B7 VCCA E12 I/O B8 I/O E13 VCCI B9 I/O E14 I/O B10 VCCI F1 I/O B11 I/O F2 I/O B12 I/O F3 VCCI B13 I/O F4 I/O B14 I/O F5 GND C1 I/O F10 GND C2 TMS F11 I/O C3 I/O F12 GND/LP1 C4 I/O F13 VCCA C5 I/O F14 I/O C6 I/O G1 VCCA C7 PRA, I/O G2 I/O C8 CLKB G3 I/O C9 I/O G4 I/O C10 I/O G5 I/O C11 I/O G10 GND C12 GND G11 I/O C13 I/O G12 I/O C14 I/O G13 I/O D1 I/O G14 VCCA D2 I/O H1 I/O D3 TDI, I/O H2 I/O D4 I/O H3 TRST, I/O D5 I/O H4 I/O Please read the VSV and LP pin descriptions for restrictions on their use.
H5 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3
GND GND I/O I/O I/O I/O I/O GND I/O VCCI GND I/O VCCI VSV1 I/O I/O I/O VSV1 I/O VCCI I/O I/O I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O HCLK I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O
M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC NC NC GND I/O I/O
30
v3.0
e X F a m il y F P GA s
Li s t o f C ha ng e s
The following table lists critical changes that were made in the current version of the document.
Previous version Changes in current version (v3.0) The "Recommended Operating Conditions" on page 8 has been changed. The "3.3V Electrical Specifications" on page 9 has been updated. v2.0.1 The "5.0V Electrical Specifications" on page 9 has been updated. The "Total Dynamic Power (mW)" on page 11 is new. The System Power at 5%, 10%, and 15% Duty Cycle is new. The "eX Timing Model*" on page 13 has been updated. The I/O Features table, Table 1 on page 5, was updated. The table, "2.5V LP/Sleep Mode Specifications Typical Conditions, VCCA, VCCI = 2.5V, TJ = 25 C" on page 6, was updated. "Typical eX Standby Current at 25C" on page 8 is a new table. The table in the section, "Package Thermal Characteristics" on page 12 has been updated for the 49-Pin CSP. Advanced v0.4 The "eX Timing Model*" on page 13 has been updated. The timing numbers found in, "eX Family Timing Characteristics" on page 16 have been updated. The VSV pin has been added to the "Pin Description" on page 20. Please see the following pin tables for the VSV pin and an important footnote including the pin: "64-Pin TQFP" on page 22,"100-TQFP" on page 24,"49-Pin CSP" on page 25,"128-CSP" on page 27, and "180-Pin CSP" on page 30. The figure, "100-Pin TQFP (Top View)" on page 23 has been updated. Advanced v0.3 In the Product Profile table, the Maximum User I/Os for eX64 was changed to 84. The Mechanical Drawings section has been removed from the data sheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site. A new section describing Clock Resources has been added. A new table describing I/O Features has been added. The Pin Description section has been updated and clarified. The original Electrical Specifications table was separated into two tables (2.5V and 3.3/5.0V). In both tables, several different currents are specified for VOH and VOL. Advanced v0.2 page 5 page 6 page 21 Page 8 and 9 Page page 8 page 9 page 9 page 11 page 11 page 13 page 5 page 6 page 8 page 11 page 12 pages 15-18 page 18 pages- 21, 23, 24, 26, 27, 29 page 22 page 1
In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100. page 1
A new table listing 2.5V low power specifications and associated power graphs were page 9 added. Pin functions for eX256 TQ100 have been added to the 100-TQFP table. A CS49 pin drawing and pin assignment table including eX64 and eX128 pin functions have been added. A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin functions have been added. A CS180 pin drawing and pin assignment table for eX256 pin functions have been added. page 25 page 26 pages 26-27 pages 27, 31 pages 14-15
Advanced v.1
The following table note was added to the eX Timing Characteristics table for clarification: Clock skew improves as the clock network becomes more heavily loaded.
v3.0
31
e X F a m il y F P GA s
D at a S he et Ca t e g o r i e s
In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. Product Briefs are modified versions of data sheets. Data sheets are marked as "Advanced," "Preliminary," and "Web-only." The definition of these categories are as follows:
P rod uct B ri ef
The product brief is a modified version of an Advanced data sheet containing general product information. This brief summarizes specific device and family information for non-release products.
Adv anc ed
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
P rel im i nar y
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
Unm ar ked (pr odu ct ion)
The data sheet contains information that is considered to be final.
W eb- only V er si ons
Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting the data sheet so customers have the latest information, but we are not printing the version because some information is going to change shortly after posting.
32
v3.0
e X F a m il y F P GA s
v3.0
33
e X F a m il y F P GA s
34
v3.0
e X F a m il y F P GA s
v3.0
35
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd. Maxfli Court, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668
5172154-4/12.01

▲Up To Search▲

Price & Availability of EX1B28-FCS100I

	To Download EX1B28-FCS100I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .